Exemplary embodiments of the present invention relate to an impedance code generation circuit, which generates an impedance code for impedance matching, and an integrated circuit including the same.
A variety of integrated circuits are implemented with integrated circuit chips, such as CPUs, memories, and gate arrays. Such integrated circuits are incorporated into a variety of electrical products, such as personal computers, servers, and workstations. In most cases, integrated circuits include reception circuits configured to receive a variety of external signals through input pads, and output circuits configured to provide a variety of internal signals through output pads to external circuits.
Meanwhile, as the operating speeds of electrical products increase, swing widths of signals transferred between integrated circuits are gradually reduced in order to minimize delay time necessary for signal transfer. However, as the swing widths of the signals are reduced, the influence of external noises increases, and signal reflection at interface terminals due to impedance mismatching becomes more severe. The impedance mismatching is generally caused by external noises or variations in a power supply voltage, operating temperature, or fabrication process. The impedance mismatching may make it difficult to transfer data at high speed and may distort output data outputted from data output terminals of the integrated circuit. Therefore, in a case where the reception circuit of the integrated circuit receives the distorted output signals through the input terminals, setup/hold fail or incorrect determination of input levels may occur frequently.
In order to address the above concerns, memory devices requiring high-speed operations have adopted impedance matching circuits, called on-die termination (ODT) devices, in the vicinity of pads inside integrated circuit chips. In a typical ODT scheme, a source termination is performed at a transmission side by an output circuit, and a parallel termination is performed at a reception side by a termination circuit coupled in parallel to the reception circuit which is coupled to an input pad.
A ZQ calibration refers to a procedure of generating impedance codes which change according to variations of process, voltage, and temperature (PVT) conditions. A termination impedance value is adjusted using impedance codes generated as a result of the ZQ calibration. Generally, a pad to which an external resistor, serving as a calibration reference, is coupled is referred to as a ZQ pad. For this reason, the term “ZQ calibration” is widely used.
Hereinafter, an impedance code generation circuit (also called a calibration circuit) for generating an impedance code will be described below.
FIG. 1 is a configuration diagram of a known impedance code generation circuit.
Referring to FIG. 1, the known impedance code generation circuit includes a reference voltage generation unit 101, comparators 102 and 103, a hold signal generation unit 104, a counter 105 and an impedance unit 106.
The reference voltage generation unit 101 generates two reference voltages VREF1 and VREF2. The two reference voltages VREF1 and VREF2 have voltage levels according to the following equations: VREF1=target voltage+α and VREF2=target voltage−α. The target voltage refers to a voltage that a calibration node ZQ should finally have. In general, the target voltage is VDD/2, where VDD is a power supply voltage. Thus, the reference voltage VREF1 has a voltage level of VDD/2+α, and the reference voltage VREF2 has a voltage level of VDD/2−α. The value of α determines the margin of the calibration operation.
The impedance unit 106 and a reference resistor 107 are coupled to the calibration node ZQ. The reference resistor 107 is a resistor for reference of the calibration operation. In general, the reference resistor 107 has a resistance of 240Ω. The voltage of the calibration node ZQ is reduced as the total impedance (resistance) value of the impedance unit 106 increases, and the voltage of the calibration node ZQ is increased as the total impedance (resistance) value of the impedance unit 106 decreases. For example, when the total impedance value of the impedance unit 106 is greater than the resistance value of the reference resistor 107, the calibration node ZQ has a voltage lower than VDD/2. When the total impedance value of the impedance unit 106 is less than the resistance value of the reference resistor 107, the calibration node ZQ has a voltage higher than VDD/2.
The comparator 102 compares the voltage of the calibration node ZQ with the reference voltage VREF1 and generates a comparison signal UP/DN1, and the comparator 103 compares the voltage of the calibration node ZQ with the reference voltage VREF2 and generates a comparison signal UP/DN2.
The hold signal generation unit 104 deactivates a hold signal HOLD when the comparison signal UP/DN1 and the comparison signal UP/DN2 have the same value, and activates the hold signal HOLD when the comparison signal UP/DN1 and the comparison signal UP/DN2 have different values.
The counter 105 detects the comparison signal UP/DN1 in response to the hold signal HOLD and generates binary impedance codes CODE<0:4>. The generation of the impedance codes CODE<0:4> is performed by increasing or decreasing the values of the impedance codes CODE<0:4> according to a logic level of the comparison signal UP/DN1. The operation of the counter 105 is performed when the hold signal HOLD is in a deactivated state. The operation of the counter 105 is stopped when the hold signal HOLD is activated. Stopping the operation of the counter 105 means that the impedance codes CODE<0:4> are not changed.
The impedance codes CODE<0:4> generated from the counter 105 turn on/off parallel resistors within the impedance unit 106 and determine the total impedance value of the impedance unit 106.
The operation of the known impedance code generation circuit will be described below. The change in the impedance codes CODE<0:4> causes the change in the impedance value of the impedance unit 106. In addition, the changed impedance value of the impedance unit 106 changes the voltage of the calibration node ZQ. Likewise, the changed voltage of the calibration node ZQ again changes the impedance codes CODE<0:4>. Such an operation is repetitively performed until the hold signal HOLD is activated. The activation of the hold signal HOLD means that the voltage of the calibration node ZQ becomes higher than the reference voltage VREF2 and lower than the reference voltage VREF1. That is, due to the repetitive operations, the total impedance value of the impedance unit 106 becomes substantially equal to the resistance value of the reference resistor 107.
The impedance codes CODE<0:4> generated from the impedance code generation circuit adjusts an impedance value of a termination unit (not shown) which is configured in a structure similar to that of the impedance unit 106. As a result, even though PVT conditions vary, the termination unit can have an exact impedance value and terminate an interface node (a node through which signals and data are inputted and outputted).
FIG. 2 is a graph showing the change in the impedance codes CODE<0:4> and the change in the impedance value of the impedance unit 106.
In the graph of FIG. 2, the value of the impedance codes CODE<0:4> decreases (i.e., approaches (1,1,1,1,1)) toward the right side on an X axis, and the value of the impedance codes CODE<0:4> increases (i.e., approaches (0,0,0,0,0)) toward the left side.
As can be seen from the graph of FIG. 2, the change in the impedance codes CODE<0:4> and the change in the impedance value of the impedance unit 106 are not linear (i.e., nonlinear). That is, as the impedance codes CODE<0:4> change by 1 step, as shown in the left side of the graph, the impedance value of the impedance unit 106 greatly changes. However, as the impedance codes CODE<0:4> changes by 1 step toward the right side of the graph, the impedance value of the impedance unit 106 slightly changes.
FIG. 3 illustrates the procedure in which the voltage of the calibration node ZQ converges between the first reference voltage VREF1 and the second reference voltage VREF2 according to the operation of the impedance code generation circuit.
Referring to FIG. 3, as the operation of the impedance code generation circuit is in progress, the voltage of the calibration node ZQ approaches the level between the first reference voltage VREF1 and the second reference voltage VREF2. A concern arises when the change in the impedance value of the impedance unit 106 per 1 step change of the impedance codes CODE<0:4> is small and the voltage of the calibration node ZQ is between the first reference voltage VREF1 and the second reference voltage VREF2, as indicated by reference numeral 301. In this case, the final value of the impedance codes CODE<0:4> may change according to noise components applied to the comparators 102 and 103, and the impedance code generation circuit may be hindered from generating the exact impedance codes CODE<0:4>.
In order to prevent the case indicated by reference numeral 301, a method for reducing the voltage difference between the first reference voltage VREF1 and the second reference voltage VREF2 may be used. However, such a method may be disadvantageous in that the voltage of the calibration node ZQ may not converge to the target voltage in a period in which the impedance value of the impedance unit 106 greatly changes with 1-step change of the impedance codes CODE<0:4>.